Semiconductor devices (for example, dynamic random access memory (DRAM) devices), are shrinking in the sense that smaller devices are being manufactured that are able to handle larger volumes of data and faster data transfer rates. Semiconductor manufacturers have been moving toward chip-scale packages (CSP) for semiconductor components having a small size and fine pitch wiring.
An exemplary CSP is shown in FIG. 1 as a board-on-chip (BOC) package 10. The package comprises a semiconductor component 12, such as an integrated circuit chip (or die), and accordingly the package can be referred to as a semiconductor package.
The package 10 comprises an interposer 14 utilized to support the semiconductor component 12. The shown interposer comprises a board 15, dielectric (i.e., electrically insulative) material 20 on one side of the board and circuitry 17 on another side of the board. Board 15 can be, for example, a glass weave material. Chip 12 is attached to the board 15 through an adhesive structure 16. The adhesive structure can be, for example, a cured glue, paste, or other polymeric matrix. As another example, the adhesive structure can be a tape. Such tape can have one side adjacent board 15 and an opposing side adjacent integrated circuit die 12, and adhesive can be along both of the opposing sides of the tape.
Dielectric material 20 is patterned to have a plurality of openings extending therethrough to the circuitry 17. Material 20 can comprise, for example, a photomask material, such as, for example, a dry film photomask. If material 20 is a photomask material, the material 20 can be patterned by photolithography. Specifically, the material can be patterned by exposing the material to a pattern of radiation and subsequently utilizing a developing solvent to impart the desired pattern within material 20.
A series of contact pads 30 are provided within the openings in dielectric material 20, and specifically are provided along a surface of circuitry 17 which is exposed within the openings. The contact pads 30 comprise a first conductive material 32 adjacent circuitry 17, and a second conductive material 34 over the first conductive material. Typically, conductive material 32 will be a nickel-containing material, and accordingly can comprise, consist essentially of, or consist of nickel; and material 34 will be a gold-containing material, and accordingly can comprise, consist essentially of, or consist of gold.
The contact pads are utilized for forming electrical contact to circuitry external of the contact pads. Solder balls 36 are shown attached to some of the contact pads, and the solder balls can then be utilized for electrically connecting the solder pads with other circuitry (not shown) external of the contact pads.
A pair of contact pad locations 40 and 42 are shown associated with integrated circuit die 12. Contact pad locations 40 and 42 comprise the nickel-containing material 32 and gold-containing material 34 of contact pads 30, but it is to be understood that contact pad locations 40 and 42 can also comprise other constructions. A pair of wires 44 and 46 are shown extending from contact pad locations 40 and 42, respectively, to a pair of the contact pads 30. The wires connect circuitry associated with integrated circuit die 12 to the circuitry of patterned conductive material 17, and can be referred to as wire bonds.
A slit 50 extends through the interposer 14, and the wires 44 and 46 extend through such slit to make the electrical contact with the contact pads 30.
An encapsulant 60 is provided within the slit 50, and over the wires 44 and 46 to protect the wires of package 10. Similarly, an encapsulant 62 is provided over integrated circuit die 12, adhesive structure 16 and board 15 to provide a protective covering over the semiconductor package.
The shown package of FIG. 1 is but one of several types of packages that can be formed in accordance with prior art methodologies. For instance, although the openings extending through insulative material 20 are shown to be wider than the contact pads (consistent with non-solder mask defined (NSMD) technologies), the openings could also be formed to be smaller than the contact pads (consistent with solder mask defined (SMD) pad technologies).
The package design of FIG. 1 can have various problems associated with the utilization of the interposer 14. Such problems can include size limitations imposed by the size of the interposer. The problems can also include negative performance properties induced by the interposer through, for example, adsorption of moisture by the interposer and/or outgassing of materials from the interposer. Accordingly, it is desired to develop new semiconductor packages.